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| DATA SHEET MOS INTEGRATED CIRCUIT PD705101 V831TM 32-BIT MICROPROCESSOR DESCRIPTION The PD70501 (V831) is a 32-bit RISC microprocessor for embedded control applications, with a high-performance 32-bit V830TM processor core and many peripheral functions such as a DRAM/ROM controller, 4-channel DMA controller, real-time pulse unit, serial interface, and interrupt controller. In addition to high interrupt response speed and optimized pipeline structure, the V831 offers sum-of-products operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia functions, and therefore, can provide high performance in multimedia systems such as internet/intra-net systems, car navigation systems, high-performance televisions, and color FAXes. Detailed explanations of the functions, etc. are given in the following user's manuals. Be sure to read the manuals before designing your systems. V831 User's Manual -Handware V830 FamilyTM : U12273E User's Manual -Architecture : U12496E * * : 4 KB : 4 KB : 4 KB : 4 KB : 1 cycle : 32 bits x 32 : 4 GB each * * * * * DMA controller : 4 channel FEATURES * CPU function * V830-compatible instructions * Instruction cache * Instruction RAM * Data cache * Data RAM * Minimum number of instruction execution cycles * Number of general purpose registers * Memory space and I/O space * Interrupt/exception function * Non-maskable : External input : 1 * Maskable : External input : 8 (of which 4 are multiplexed with internal sources) Internal source: 11 types * * * Bus control function Wait control function Memory access control function Serial interface function * Asynchronous serial interface (UART): 1 channel * Clocked serial interface (CSI) Timer/counter function * 16-bit timer/event counter : 1 channel * 16-bit interval timer Port function Standby function Debug function * Debug-dedicated synchronous serial interface * Trace-dedicated interface : 1 channel : 1 channel : 1 channel : 3 I/O ports : HALT and STOP modes : 1 channel * Dedicated baud rate generator (BRG) : 1 channel Clock generation function : PLL clock synthesizer The information in this document is subject to change without notice. Document No. U12979EJ1V0DS00 (1st edition) Date Published January 1998 N Printed in Japan (c) 1998 PD705101 ORDERING INFORMATION Part Number Package 160-pin plastic LQFP (fine pitch) (24 x 24 mm) PD705101GM-100-8ED PIN CONFIGURATION (TOP VIEW) * 160-pin plastic LQFP (fine pitch) (24 x 24 mm) PD705101GM-100-8ED GND D2 D3 D4 D5 D6 D7 D8 VDD GND D9 D10 D11 VDD GND D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 VDD GND D22 D23 D24 VDD GND D25 D26 D27 D28 D29 D30 D31 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 VDD D1 D0 LLCAS LUCAS ULCAS UUCAS RAS OE WE A1 GND VDD GND VDD A2 A3 A4 A5 A6 A7 A8 A9 GND VDD A10 A11 GND VDD A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 GND 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VDD CLKOUT TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3 DDI DCK DMS DDO A22 A23 GND VDD IOWR IORD BCYST READY HLDRQ HLDAK CS1 CS2 GND VDD CS3 CS4 CS5 GND VDD CS6 CS7 INTP10/TO10 INTP12/TO11 INTP11 INTP13 TI TCLR INTP00 INTP01 GND 2 GND LLMWR LUMWR ULMWR UUMWR MRD TXD RXD GND VDD PORT2/SI PORT1/SO PORT0/SCLK VDD_PLL X1 X2 GND_PLL GND VDD GND VDD RESET DRST NMI BT16B GND VDD GND DMAAK0 DMAAK1 DMAAK2 DMAAK3 DMARQ0 DMARQ1 DMARQ2 DMARQ3 TC/REFRQ INTP03 INTP02 VDD 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PD705101 PIN NAMES A1-A23 BCYST BT16B CLKOUT CS1-CS7 D0-D31 DCK DDI DDO : Address Bus : Bus Cycle Start : Boot Bus Size 16 bit : Clock Out : Chip Select : Data Bus : Debug Clock : Debug Data Input : Debug Data Output NMI OE PORT0-PORT2 RAS READY REFRQ RESET RXD SCLK SI SO TC TCLR TI TO10, TO11 : Non-Maskable Interrupt Request : Output Enable : Port : Row Address Strobe : Ready : Refresh Request : Reset : Receive Data : Serial Clock : Serial Input : Serial Output : Terminal Count : Timer Clear : Timer Input : Timer Output : Trace Data DMAAK0-DMAAK3 : DMA Acknowledge DMARQ0-DMARQ3: DMA Request DMS DRST GND GND_PLL HLDAK HLDRQ : Debug Mode Select : Debug Reset : Ground : PLL Ground : Hold Acknowledge : Hold Request TRCDATA0-TRCDATA3 TXD ULCAS ULMWR UUCAS UUMWR VDD VDD_PLL WE X1, X2 : Transmit Data : Upper Lower Column Address Strobe : Upper Lower Memory Write : Upper Upper Column Address Strobe : Upper Upper Memory Write : Power Supply : PLL Power Supply : Write Enable : Crystal Oscillator INTP00-INTP03, INTP10-INTP13 : Interrupt Request From Peripheral IORD IOWR LLCAS LLMWR LUCAS LUMWR MRD : I/O Read : I/O Write : Lower Lower Column Address Strobe : Lower Lower Memory Write : Lower Upper Column Address Strobe : Lower Upper Memory Write : Memory Read 3 PD705101 BLOCK DIAGRAM DCK DMS DDI DDO TRCDATA0 - TRCDATA3 IOWR IORD DCU UUMWR, ULMWR, LUMWR, LLMWR MRD READY BT16B CG BCU BCYST CS1-CS7 A1-A23 SYU V830 core D0-D31 HLDRQ DRST X1 X2 CLKOUT RESET NMI TI, TCLR INTP10/TO10, INTP12/TO11 RPU HLDAK RAS UUCAS, ULCAS, LUCAS, LLCAS INTP11, INTP13 INTP00 - INTP03 ICU WE OE REFRQ/TC P10 PORT0/SCLK PORT1/SO PORT2/SI TXD RXD CSI BRG UART DMAC DMARQ0 - DMARQ3 DMAAK0 - DMAAK3 4 PD705101 CONTENTS 1. 2. 3. 4. 5. 6. 7. PIN FUNCTIONS LIST ......................................................................................................................... 6 INTERNAL UNITS ................................................................................................................................ 8 CPU FUNCTION ................................................................................................................................. 10 INTERRUPT/EXCEPTION PROCESSING FUNCTION ..................................................................... 11 BUS CONTROL FUNCTION .............................................................................................................. 13 WAIT CONTROL FUNCTION ............................................................................................................. 13 MEMORY ACCESS CONTROL FUNCTION ...................................................................................... 14 7.1 7.2 DRAM Control Function ............................................................................................................................ 14 Page-ROM Control Function ..................................................................................................................... 15 8. 9. DMA FUNCTION ................................................................................................................................ 16 SERIAL INTERFACE FUNCTION ...................................................................................................... 18 9.1 9.2 9.3 Asynchronous Serial Interface (UART) ................................................................................................... 18 Clocked Serial Interface (CSI) ................................................................................................................... 20 Baud Rate Generator (BRG) ...................................................................................................................... 21 9.3.1 Configuration and function ................................................................................................................ 21 10. TIMER/COUNTER FUNCTION .......................................................................................................... 22 11. PORT FUNCTION .............................................................................................................................. 25 12. CLOCK GENERATION FUNCTION ................................................................................................... 27 13. STANDBY FUNCTION ........................................................................................................................ 28 14. RESET/NMI CONTROL FUNCTION .................................................................................................. 30 15. INSTRUCTIONS ................................................................................................................................. 31 15.1 Instruction Format ..................................................................................................................................... 31 15.2 Instructions (Listed Alphabetically) ......................................................................................................... 33 16. ELECTRICAL SPECIFICATIONS ...................................................................................................... 43 17. PACKAGE DRAWINGS ...................................................................................................................... 65 18. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 66 5 PD705101 1. PIN FUNCTIONS LIST (1/2) Pin Name D0-D31 A1-A23 UUCAS ULCAS LUCAS LLCAS RAS UUMWR ULMWR LUMWR LLMWR MRD WE OE IORD IOWR REFRQ CS1, CS2, CS7 CS3-CS6 BCYST BT16B READY DMARQ0-DMARQ3 DMAAK0-DMAAK3 TC RXD TXD SI SO SCLK TI TCLR TO10 TO11 Output Input Output Input Output I/O Input Output Input I/O 3-state I/O 3-state output Data bus Address bus Column address strobe (most significant byte) Column address strobe (most significant byte) Column address strobe (third byte) Column address strobe (least significant byte) Row address strobe/chip select Memory write strobe (most significant byte) Memory write strobe (second byte) Memory write strobe (third byte) Memory write strobe (least significant byte) Memory read strobe DRAM write strobe DRAM read strobe I/O read strobe I/O write strobe DRAM refresh request Memory chip select Memory chip select / I/O chip select Bus cycle start Specifies bus size on boot Enables end of bus cycle DMA request (CH0 through CH3) DMA enable (CH0 through CH3) DMA transfer end UART data input UART data output CSI data input CSI data output CSI clock I/O Timer 1 count clock input Timer 1 clear, start RPU pulse output INTP10 INTP12 PORT2 PORT1 PORT0 - - REFRQ - - TC - - - - - - - Function Multiplexed Pin - - - - - - - - - - - - - - - - 6 PD705101 (2/2) Pin Name INTP10 INTP11 INTP12 INTP13 INTP00-INTP03 HLDRQ HLDAK NMI RESET PORT0 PORT1 PORT2 X1 - Connects crystal resonator. (Opened when external clock is input.) Connects crystal resonator or inputs external clock. Bus clock output Debug clock input Debug data input 3-state output Input Debug data output Debug mode select Reset input (debug module) Output Trace data output I/O Output Input Bus request Bus enable Non-maskable interrupt request System reset Port SCLK SO SI - TO11 - - - - - - Input I/O Interrupt request Function Multiplexed Pin TO10 - X2 CLKOUT DCK DDI DDO DMS DRST TRCDATA0TRCDATA3 VDD GND VDD_PLL GND_PLL Input Output Input - - - - - - - - - Positive power supply Ground potential Positive power supply for PLL (internal clock generator) Ground potential for PLL (internal clock generator) - - - - 7 PD705101 2. INTERNAL UNITS (1) Bus control unit (BCU) Controls the address bus, data bus, and control bus pins. The major functions of BCU are as follows: (a) Bus arbitration Arbitrates the bus mastership among bus masters (CPU, DRAMC, DMAC, and external bus masters). The bus mastership can be changed after completion of the bus cycle under execution, and in an idle state. (b) Wait control Controls eight areas in the 16M-byte space corresponding to RAS and seven chip select signals (CS1 through CS7). Generates chip select signals, controls wait states, and selects the type of bus cycle. (c) DMA controller Generates RAS and four CAS signals, and controls access to DRAM. The hyper page mode of DRAM is supported and DRAM can be accessed in two types of cycle: normal access (off-page) and hyper page (onpage). (d) ROM controller Accessing ROM with page access function is supported. The bus cycle immediately before and addresses are compared, and wait states are controlled in the normal access (off-page) and page access (on-page) modes. A page width of 8 bytes to 16 bytes can be supported. (2) Interrupt controller (ICU) Services maskable interrupt requests (INTP00 through INTP03, and INTP10 through INTP13) from internal peripheral hardware and external sources. The priorities of these interrupt requests can be specified in units of four groups, and edge-triggered or level-triggered interrupts can be nested. (3) DMA controller (DMAC) Transfers data between memory and I/O in the place of the CPU. The transfer type is 2-cycle transfer. Two transfer modes, single transfer and demand transfer, are available. (4) Serial interface (UART/CSI/BRG) One asynchronous serial interface (UART) channel and one clocked serial interface (CSI) channel is provided. As the serial clock source, the output of the baud rate generator (BRG) and the bus clock can be selected. (5) Real-time pulse unit (RPU) Provides timer/counter functions. The on-chip 16-bit time/event counter and 16-bit interval timer can be used to calculate pulse intervals and frequencies, and to output programmable pulses. (6) Clock generator (CG) A frequency three times higher than that of an oscillator connected to the X1 and X2 pins is supplied as the operating clock of the CPU. In addition, a bus clock (with the same cycle as the input clock) is also supplied as the operating clock of the peripheral units. An external clock can be also input instead of connecting an oscillator. (7) Port (PIO) Provides port functions. Three I/O ports are available. The pins of these ports can be used as port pins or serial control pins. 8 PD705101 (8) System control unit (SYU) A circuit that rejects noise on the RESET signal (input)/NMI signal (input) is provided. (9) Debug control unit (DCU) A circuit to realize mapping and trace functions is provided to implement basic debugging functions. 9 PD705101 3. CPU FUNCTION The features of the CPU function are as follows: * High-performance 32-bit architecture for embedded control applications * Cache memory Instruction cache : 4K bytes Data cache * Internal RAM Instruction RAM : 4K bytes Data RAM : 4K bytes * 1-clock pitch pipeline structure * 16-/32-bit length instruction format * Address/data separated type bus * 4GB linear address * Thirty-two 32-bit general register * Register/flag hazard interlock is handled by hardware * 16 levels of interrupt response : 4K bytes * 16-bit bus fixed function * 16-bit bus system can be constructed * Ideal instructions for any application field: * Sum-of-products operation * Saturation operation * Branch prediction * Concatenation shift * Block transfer instruction 10 PD705101 4. INTERRUPT/EXCEPTION PROCESSING FUNCTION The features of the interrupt/exception processing function are as follows: * Interrupt * Non-maskable interrupt : 1 source * Maskable interrupt : 15 sources * Priority of the programmable interrupt can be specified in four levels * Nesting interrupt can be controlled according to the priority * Mask can be specified for each maskable interrupt request * Valid edge of an external interrupt request can be specified * Noise rejection circuit provided for the non-maskable interrupt pin (NMI) * Exception * Software exception : 32 sources * Exception trap : 4 sources The interrupt/exception sources are shown in Tables 4-1 and 4-2. Table 4-1. Reset/Non-maskable Interrupt/Exception Source List Source of Interrupt/Exception NameNote 1 Reset Non-maskable Software exception Interrupt Interrupt Exception RESET NMI TRAP 1nH TRAP 0nH Exception trap Exception NMI FAULT I-OPC Cause Reset input NMI input TRAP instruction TRAP instruction Dual exception Fatal exception Illegal instruction code Zero division Exception Code (ECR) FFF0H FFD0H FFBnH FFAnH Note 4 Not affected FF90H Handler Address FFFFFFF0H Restore PCNote 2 Undefined Type Classification FFFFFFD0H next PCNote 3 FFFFFFB0H FFFFFFA0H FFFFFFD0H current PC FFFFFFE0H FFFFFF90H next PC DIV0 FF80H FFFFFF80H Notes 1. Handler names used in development tools or software. 2. The PC value saved to EIPC/FEPC/DPC when interrupt/exception processing is started. 3. Execution of all instructions cannot be stopped by an interrupt. 4. The exception code of an exception causing a dual exception. Remark n = 0H to FH 11 PD705101 Table 4-2. Maskable Interrupt List InClassifiType cation Group Group Priority Mask- Interrupt GR3 able 3 2 1 0 GR2 3 2 1 0 GR1 3 2 Source of Interrupt Name RESERVED Reserved INTOV1 INTSER INTP03 INTSR INTST INTCSI INTP02 INTDMA INTP10/ INTCC10 INTP11/ INTCC11 INTP01 INTCM4 INTP12/ INTCC12 INTP13/ INTCC13 INTP00 Timer 1 overflow UART receive error INTP03 pin input UART receive end UART transmit end Cause Unit - RPU UART External UART UART Handler AddressNote 3 HCCW.IHA=0 HCCW.IHA=1 Exception Code FEF0H Restore PCNote 1 FFFFFEF0H FE0000F0H next FEE0H FFFFFEE0H FE0000E0H PCNote 2 FED0H FFFFFED0H FE0000D0H FEC0H FFFFFEC0H FE0000C0H FEB0H FFFFFEB0H FE0000B0H FEA0H FFFFFEA0H FE0000A0H FE90H FE80H FE70H FE60H FFFFFE90H FE000090H FFFFFE80H FE000080H FFFFFE70H FE000070H FFFFFE60H FE000060H CSI transmit/receive end CSI INTP02 pin input DMA transfer end INTP10 pin input/ coincidence of CC10 INTP11 pin input/ coincidence of CC11 INTP01 pin input Coincidence of CM4 INTP12 pin input/ coincidence of CC11 INTP13 pin input/ coincidence of CC13 INTP00 pin input External DMAC External/ RPU 1 External/ FE50H RPU External RPU FE40H FE30H FFFFFE50H FE000050H 0 GR0 3 2 FFFFFE40H FE000040H FFFFFE30H FE000030H FFFFFE20H FE000020H External/ FE20H RPU External/ FE10H RPU External FE00H 1 FFFFFE10H FE000010H 0 FFFFFE00H FE000000H Notes 1. The PC value saved to EIPC when interrupt processing is started. 2. Execution of all instructions cannot be stopped by an interrupt. 3. FFFFFEn0H can be selected as a handler address when HCCW.IHA = 0, and FE0000n0H can be selected when HCCW.IHA = 1 (N = 0H to FH). Caution The exception codes and handler addresses of the maskable interrupts shown above are the values if the default priority is used. 12 PD705101 5. BUS CONTROL FUNCTION The features of the bus control function are as follows: * * * * * Directly connects to EDO DRAM, Page-ROM, SRAM (ROM), or I/O CAS access with 1 bus clock minimum DRAM byte access control with four CAS signals Wait control by READY signal 32-/16-bit bus width can be set every CS space * When the 16-bit memory or I/O are accessed by data bus, the external data bus width can be set by the data bus width control register (DBC). 6. WAIT CONTROL FUNCTION The features of the wait control function are as follows: * * * Controls 8 blocks in accordance with I/O and memory spaces Linear address space of each block: 16M bytes Bus cycle select function Block 0 Blocks 1 and 2 Blocks 3 through 6 Block 7 : EDO DRAM : SRAM (ROM) : I/O or SRAM (ROM) selectable : Page-ROM or SRAM (ROM) selectable * * Data bus width select function Data bus width selectable between 32 bits and 16 bits for each block Wait control function Block 0 Blocks 5 and 6 : Can control EDO DRAM access timing : 0 to 15 wait states Blocks 1 through 4 and 7 : 0 to 7 wait states * Idle state insertion function 0 to 3 states for each block (bus clock) 13 PD705101 7. MEMORY ACCESS CONTROL FUNCTION The features of the memory access control function are as follows: * DRAM control function * Generates RAS, LLCAS, LUCAS, ULCAS, UUCAS, REFRQ, OE, and WE signals * Address multiplex: 8, 9, or 10 bits * Timing control of DRAM access CAS access period : 1 or 2 bus clocks selectable RAS-CAS delay period : 1.5 or 2.5 bus clocks selectable RAS precharge period : 2 or 3 bus clocks selectable * CBR refresh and CBR self-refresh functions * Page-ROM control function * Page size : 8 or 16 bytes * Wait control during page access: 0 or 1 wait states 7.1 DRAM Control Function The BCU generates RAS, LLCAS, LUCAS, ULCAS, UUCAS, REFRQ, OE, and WE signals and controls access to the DRAM. Addresses are output to the DRAM from the address pins by multiplexing row and column addresses. The connected DRAM must be of x8 bits or more and have a hyper page mode (EDO). The refresh mode is a CAS-before-RAS (CBR) mode, and the refresh cycle can be arbitrarily set. CBR self refresh is performed in the STOP mode. (1) Address multiplex function An address is multiplexed as shown in Figure 7-1 when a row and column addresses are output in the DMA cycle, depending on the value of the DAW bit of the DRAM configuration register (DRC). In this figure, a1 through a23 indicate the address output by the CPU, and A1 through A23 indicate the address pins of the V831. 14 PD705101 Figure 7-1. Output of Row Address and Column Address Address pins A23 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 DAW = 10 a23 a15 a14 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 DAW = 01 a23 a15 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 DAW = 00 a23 a15 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 Column address a23 a1 (2) Decision of on-page/off-page If the RAS signal is active when page access is enabled because the HPAE bit of the DRAM configuration register (DRC) is 1, whether the DRAM access to be started is in the same page as the previous DRAM access is decided. Table 7-1 shows the relation between an address to be compared and address shift. Table 7-1. Address Compared by on-page/off-page Decision Data Bus Width 16 bits 8 9 10 a23-a9 a23-a10 a23-a11 32 bits a23-a10 a23-a11 a23-a12 Address Shift (3) Refresh function The BCU can automatically generate the distributed CBR refresh cycle necessary for refreshing the external DRAM. Whether refreshing is enabled or disabled and the refresh interval are set by the refresh control register (RFC). The BCU has a refresh request queue that can store refresh requests up to seven times. 7.2 Page-ROM Control Function The BCU controls page access to the Page-ROM. Page access to the Page-ROM is valid during burst access. The page size (8 bytes/16 bytes) and the number of wait states (0 wait/1 wait) during page access can be set by using the Page-ROM configuration register (PRC). 15 PD705101 8. DMA FUNCTION The features of the DMA function are as follows: * * * * * * Four independent DMA channels Transfer unit: Bytes, half words (2 bytes), words (4 bytes) Maximum number of transfers: 16,777,216 (224) times Transfer type: 2-cycle transfer Two transfer modes * Single transfer mode * Demand transfer mode Transfer request * External DMARQ pin (x4) * Request from internal peripheral hardware (serial interface (x3 channels) and timer) * Request from software * * * Transfer source and destination * Between memory and I/O * Between memory and memory Programmable wait function DMA transfer end output signal (TC) 16 PD705101 The configuration of the DMA controller (DMAC) is shown below. Figure 8-1. DMAC Block Diagram DMAC Internal I/O Bus interface ROM Internal peripheral I/O bus BCU DMA source address register (DSA) External bus RAM Address control block DMA destination address register (DDA) I/O Counter control block DMA transfer count register (DBC) I/O Channel control block DMA control register (DCHC, DC) DMARQ0 - 3 DMAAK0 - 3 INTCM4 INTDMA INTCSI INTSR INTST TC 17 PD705101 9. SERIAL INTERFACE FUNCTION The following channels are provided for the serial interface function. * * * Asynchronous serial interface (UART) : 1 channel Clocked serial interface (CSI) Baud rate generator (BRG) : 1 channel : 1 channel 9.1 Asynchronous Serial Interface (UART) The features of the asynchronous serial interface (UART) are as follows: * * * * * Full duplex communication. Receive buffer (RXB) is provided (transmit buffer (TXB) is not provided). Two-pin configuration (The UART of the V831 does not have the SCLK and CTS pins.) * TXD: Transmit data output pin * RXD: Receive data input pin Transfer rate: 150 bps to 76800 bps (bus clock: 33 MHz, with BRG) Baud rate generator Serial clock source can be selected from band rate generator output or bus clock () Receive error detection function * Parity error * Framing error * Overrun error * Three interrupt sources * Receive error interrupt (INTSER) The interrupt is generated by ORing three types of receive errors. * Receive end interrupt (INTSR) The receive end interrupt request is generated after completion of receive data transfer from the shift register to the receive buffer in the reception enabled status. * Transmit end interrupt (INTST) The transmit end interrupt is generated after completion of serial transfer of transmit data (9, 8, or 7 bits) from the shift register. The character length of the transmit/receive data is specified by the ASIM00 and ASIM01 registers. * * * Character length : 7 or 8 bits : 9 bits (with extension bit appended) Parity function : Odd, even, 0, or none Transmit stop bit : 1 or 2 bits 18 PD705101 The configuration of the asynchronous serial interface (UART) is shown below. Figure 9-1. Block Diagram of UART Internal peripheral I/O bus 16/8 8 RXB0 Receive buffer RXB0L 8 16/8 Mode register ASIM00 ASIM01 RXD Receive shift register Status register ASIS0 Transmit shift register TXS0 TXS0L TXD Receive control parity check INTSER Transmit control parity append INTST INTSR 1/16 1/16 1/2 SEL Baud rate generator Remark = bus clock (33 M to 16.7 MHz) 19 PD705101 9.2 Clocked Serial Interface (CSI) The features of the clocked serial interface (CSI) are as follows: * * * * High-speed transfer: 8.25 Mbps MAX. (bus clock: 33 MHz) Half duplex communication for transmission/reception (buffer is not provided) Character length: 8 bits External or internal clock selectable The configuration of the clocked serial interface (CSI) is shown below. Figure 9-2. Block Diagram of CSI Internal peripheral I/O bus 8 8 CSIM0 Mode register SIO0 SO latch Shift register D Q SI SO SCLK Serial clock control circuit SEL 1/2 Baud rate generator SEL 1/2, 1/4, 1/8, 1/16, 1/32 prescaler Serial clock counter Interrupt control circuit INTCSI Remark = bus clock (33 M to 16.7 MHz) 20 PD705101 9.3 Baud Rate Generator (BRG) 9.3.1 Configuration and function The serial interface can use the serial clock output by the baud rate generator or the divided value of (bus clock) as a baud rate. The serial clock source is specified by the following registers. * * * In the case of UART : Specified by the SCLS0 bit of the ASIM00 register. In the case of CSI : Specified by the CLS02 through CLS00 bits of the CSIM0 register. The baud rate generator is shared by the UART and CSI. The configuration of the baud rate generator (BRG) is shown below. Figure 9-3. Block Configuration of Baud Rate Generator (BRG) Internal peripheral I/O bus BRG0 Compare register BRCE0 BPR00 - 02 BPRM0 Serial interface (UART/CSI) TMBRG0 Internal timer Prescaler 1/2 Remark = bus clock (33 M to 16.7 MHz) 21 PD705101 10. TIMER/COUNTER FUNCTION The features of the timer/counter function are as follows: * * Measures pulse interval and frequency and outputs programmable pulse * 16-bit measurement * Can generate pulses of various shapes (interval pulse, one-shot pulse) Timer 1 * 16-bit timer/event counter * Source of count clock * Count clear pin * Interrupt source * External pulse output : 2 types (selected by dividing system clock, external pulse input) : TCLR : 5 types : 2 pins * Capture/compare register : x 4 * Timer 4 * 16-bit interval timer * Count clock selected by dividing system clock * Compare register: x 1 * Interrupt source : 1 type 22 PD705101 The configurations of timer 1 and timer 4 are shown below. Figure 10-1. Block Configuration of Timer 1 TCLR1 Edge detection Clear & start /2 /4 m m m/4 m/16 Note 1 TM1 (16 bits) TI Note 2 INTOV1 Edge detection INTCC10 INTCC11 INTP10 INTP11 INTP12 INTP13 Edge detection Edge detection Edge detection Edge detection CC10 CC11 CC12 CC13 S R S R Note 3 Note 3 Q TO10 Q Q TO11 Q INTCC12 INTCC13 Notes 1. Internal count clock 2. External count clock (TI: 4.125 MHz MAX.) 3. Reset priority Remarks 1. = bus clock (33 M to 16.7 MHz) 2. m = intermediate clock 23 PD705101 Figure 10-2. Block Configuration of Timer 4 /2 /8 m m/16 m/32 Note TM4 (16 bits) Clear & start CM4 INTCM4 Note Internal count clock Remarks 1. = bus clock (33 M to 16.7 MHz) 2. m = intermediate clock 24 PD705101 11. PORT FUNCTION The features of the port function are as follows: * * 3-bit input/output port which can be specified in 1-bit units In addition to the port function, the port can operate as the I/O of the serial interface (CSI) in the control mode * Port 0 (control mode): operates as SCLK * Port 1 (control mode): operates as SO * Port 2 (control mode): operates as SI The configurations of port 0 through 2 are shown below. Figure 11-1. Block Diagram of Port 0 Control mode register (PC) Internal peripheral I/O bus Mode register (PM) Selector SCLK output Port register (PORT) PORT0 Selector SCLK input 25 PD705101 Figure 11-2. Block Diagram of Port 1 Control mode register (PC) Internal peripheral I/O bus Mode register (PM) Selector SO Port register (PORT) PORT1 Selector Figure 11-3. Block Diagram of Port 2 Control mode register (PC) Internal peripheral I/O bus Mode register (PM) Port register (PORT) Selector PORT2 SI 26 PD705101 12. CLOCK GENERATION FUNCTION The features of the clock generation function are as follows: * Generation and control of CPU clock and bus clock supplied to each hardware unit * Bus clock () : 16.7-33 MHz (fB) * CPU clock : 50-100 MHz (3 x fB) The configuration of the clock generation function is shown below. Figure 12-1. Block Diagram of Clock Generation Function PLL synthesizer 1/6 X1 OSC X2 fB Phase comparator 200 MHz 1/2 PDF VCO 33 MHz Bus clock CPU clock 100 MHz fB : Oscillation frequency or external clock frequency : Bus clock OSC : Oscillator PFD : Phase Frequency Detector VCO : Voltage Controlled Oscillator 27 PD705101 13. STANDBY FUNCTION The following two standby modes can be used. (1) HALT mode In this mode, the clock generator (oscillation circuit and PLL synthesizer) operates, but the operating clock of the CPU is stopped. The other internal peripheral functions are supplied with the clock and continue operation. By using this mode in combination with the normal mode, the power consumption of the entire system can be reduced. (2) STOP mode In this mode, the clock generator (PLL synthesizer) is stopped and the entire system is stopped. Because the PLL synthesizer and internal peripheral functions are stopped, the power consumption can be reduced more than in the HALT mode. Because the clock output of the PLL synthesizer is stopped, make sure that sufficient time elapses after the STOP mode is released until the oscillation circuit, CPU clock, and bus clock are stabilized. The PLL circuit may require lock up time depending on the program. Table 13-1 shows the operations of the clock generator in the HALT and STOP modes. By selecting each mode as the application requires, the power consumption of the system can be efficiently reduced. Table 13-1. Operation of Clock Generator in Standby Mode Standby Mode Oscillation Circuit (OSC) PLL Synthesizer Clock Supply to Peripheral I/O Clock Supply to CPU Normal mode HALT mode STOP mode x x x x Remark : Operates x : Stopped 28 PD705101 Table 13-2. Operating Status in HALT/STOP Mode Function Oscillation circuit PLL synthesizer Bus clock CPU Port output Peripheral function Internal data A1-A23 Operating StatusNote 1 Operates Operates Operates Stops Retained Operates Stops Stops Stops STOP Mode Internal data such as registers of CPU retain status before HALT mode is set. Undefined -------- High impedance when HLDAK = 0 Undefined D0-D31 BCYST CS1-CS7 IORD, IOWR MRD, WE, OE, LLMWR, LUMWR, ULMWR, UUMWR REFRQ, LLCAS, LUCAS, ULCAS, UUCAS RAS HLDRQ CLKOUT High impedance 1 ----------------------------------- High impedance when HLDAK = 0 1 1Note 2 CBR self refreshNote 4 Note 3 Operates Not accept 0 Clock output (when clock output is not disabled) Notes 1. Each pin is in the operating status during DMA transfer. 2. Other than CBR refresh 3. The previous status is retained before CBR refresh is executed. This pin is set to "1" after CBR refresh. 4. CBR self refresh is not executed when it is disabled. In this case, the status of this pin before the STOP mode is set is retained. 29 PD705101 14. RESET/NMI CONTROL FUNCTION The features of the reset/NMI control function are as follows: * * RESET and NMI pins have noise rejection circuit that samples clock. Performs forced reset, reset mask, and NMI mask processing from debug control unit Table 14-1 shows the status of the output pins during the system reset period and immediately after reset. This status is retained during the reset period. Table 14-1. Status of Output Pin Immediately after Reset Function A1-A23 D0-D31 CS1-CS7 BCYST IORD, IOWR WE, OE LLMWR, LUMWR, ULMWR, UUMWR LLCAS, LUCAS, ULCAS, UUCAS RAS CLKOUT HLDAK DMAAK0-DMAAK3 PORT2/SI PORT1/SO PORT0/SCLK TXD DDO TRCDATA0-TRCDATA3 TC/REFRQ TO10/INTP10, TO11/INTP12 Operating Status Undefined High impedance 1 1 1 1 1 1 1 Clock output 1 1 High impedance High impedance High impedance 1 Undefined Undefined 1 High impedance 30 PD705101 15. INSTRUCTIONS 15.1 Instruction Format The V831 uses two instruction formats: 16-bit and 32-bit. The 16-bit instructions include binary operation, control, and conditional branch instructions, while the 32-bit instructions include load/store and I/O operation instructions, instructions for handling 16 bits of immediate data, and jump-and-link instructions. Some instructions contain unused fields, which must be fixed to 0, which are provided for future use. When an instruction is actually loaded into memory, its configuration is as follows: * Low-order part of each instruction format (including bit 0) Low-order address * High-order part of each instruction format (including bit 15 or 31) High-order address (1) reg-reg instruction format [FORMAT I] This instruction format has a six-bit operation code field and two general-purpose register designation fields for operand specification, giving a total length of 16 bits. 15 opcode 10 9 reg 2 54 reg 1 0 (2) imm-reg instruction format [FORMAT II] This instruction format has a six-bit operation code field, a five-bit immediate data field, and a general-purpose register designation field, giving a total length of 16 bits. 15 opcode 10 9 reg 2 54 imm 5 0 (3) Conditional branch instruction format [FORMAT III] This instruction format has a three-bit operation code field, a four-bit condition code field, a nine-bit branch displacement field (bit 0 is handled as 0 and need not be specified), and a one-bit sub-operation code, giving a total length of 16 bits. 15 98 cond disp 9 10 s s = 0 : Bcond s = 1 : ABcond 13 12 opcode s : sub-opcode 31 PD705101 (4) Medium-distance jump instruction format [FORMAT IV] This instruction format has a six-bit operation code field and a 26-bit displacement field (the lowest-order bit must be 0), giving a total length of 32 bits. 15 opcode 10 9 0 31 disp 26 16 0 (5) Three-operand instruction format [FORMAT V] This instruction format has a six-bit operation code field, two general-purpose register designation fields, and a 16-bit immediate data field, giving a total length of 32 bits. 15 opcode 10 9 reg 2 54 reg 1 0 31 imm 16 16 (6) Load/store instruction format [FORMAT VI] This instruction format has a six-bit operation code field, two general-purpose register designation fields, and a 16-bit displacement field, giving a total length of 32 bits. 15 opcode 10 9 reg 2 54 reg 1 0 31 disp 16 16 (7) Extended instruction format [FORMAT VII] This instruction format has a six-bit operation code field, two general-purpose register designation fields, and a six-bit sub-operation code field, giving a total length of 32 bits. 15 opcode 10 9 reg 2 54 reg 1 0 31 sub-opcode 26 25 RFU 16 (8) Three-register operand instruction format [FORMAT VIII] This instruction format has a six-bit operation code field, three general-purpose register designation fields, and a six-bit sub-operation code field, giving a total length of 32 bits. 15 opcode 10 9 reg 2 54 reg 1 0 31 sub-opcode 26 25 RFU 21 20 reg 3 16 (9) No-operand instruction format [FORMAT IX] This instruction format has a six-bit operation code field and a one-bit sub-operation code field, giving a total length of 16 bits. 15 opcode s : sub-opcode 10 9 RFU 10 s 32 PD705101 15.2 Instructions (Listed Alphabetically) The instructions are listed below in alphabetic order of their mnemonics. Explanation of list format Instruction ADD Operand(s) reg1, reg2 Format CY OV I * * S * Z * Function Instruction mnemonic Instruction format (See Section 15.1.) Indicates how each flag changes. - : Does not change. * : Changes. 0 : Becomes 0. 1 : Becomes 1. Abbreviations of operands Abbreviation reg1 reg2 Meaning General-purpose register (used as a source register) General-purpose register (used mainly as a destination register, but in some instructions, used as a source register) General-purpose register (used mainly as a destination register, but in some instructions, used as a source register) x bits of immediate data x-bit displacement System register number Trap handler address corresponding to trap vector reg3 immx dispx regID vector adr 33 PD705101 Instruction ABC Operand(s) disp9 Format III CY - OV - S - Z - Function High-speed conditional branch (if Carry) relative to PC. High-speed conditional branch (if Equal) relative to PC. ABGE disp9 III - - - - High-speed conditional branch (if Greater than or Equal) relative to PC. High-speed conditional branch (if Greater than) relative to PC. ABH disp9 III - - - - High-speed conditional branch (if Higher) relative to PC. High-speed conditional branch (if Lower) relative to PC. ABLE disp9 III - - - - High-speed conditional branch (if Less than or Equal) relative to PC. High-speed conditional branch (if Less than) relative to PC. High-speed conditional branch (if Negative) relative to PC. High-speed conditional branch (if Not Carry) relative to PC. High-speed conditional branch (if Not Equal) relative to PC. High-speed conditional branch (if Not Higher) relative to PC. High-speed conditional branch (if Not Lower) relative to PC. High-speed conditional branch (if Not Overflow) relative to PC. High-speed conditional branch (if Not Zero) relative to PC. High-speed conditional branch (if Positive) relative to PC. High-speed unconditional branch (Always) relative to PC. High-speed conditional branch (if Overflow) relative to PC. High-speed conditional branch (if Zero) relative to PC. Addition. reg1 is added to reg2 and the sum is written into reg2. Addition. imm5, sign-extended to a word, is added to reg2 and the sum is written into reg2. Addition. imm16, sign-extended to a word, is added to reg1, and the sum is written into reg2. ABE disp9 III - - - - ABGT disp9 III - - - - ABL disp9 III - - - - ABLT disp9 III - - - - ABN disp9 III - - - - ABNC disp9 III - - - - ABNE disp9 III - - - - ABNH disp9 III - - - - ABNL disp9 III - - - - ABNV disp9 III - - - - ABNZ disp9 III - - - - ABP disp9 III - - - - ABR disp9 III - - - - ABV disp9 III - - - - ABZ disp9 III - - - - ADD reg1, reg2 I imm5, reg2 II ADDI imm16, reg1, reg2 V 34 PD705101 Instruction AND Operand(s) reg1, reg2 Format I CY - OV 0 S Z Function AND. reg2 and reg1 are ANDed and the result is written into reg2. AND. reg1 is ANDed with imm16, zero-extended to a word, and result is written into reg2. BC BDLD disp9 [reg1], [reg2] III VII - - - - - - - - Conditional branch (if Carry) relative to PC. Block transfer. 4 words of data are transferred from external memory to built-in data RAM. BDST [reg2], [reg1] VII - - - - Block transfer. 4 words of data are transferred from built-in data RAM to external memory. Conditional branch (if Equal) relative to PC. Conditional branch (if Greater than or Equal) relative to PC. Conditional branch (if Greater than) relative to PC. BH BILD disp9 [reg1], [reg2] III VII - - - - - - - - Conditional branch (if Higher) relative to PC. Block transfer. 4 words of data are transferred from external memory to built-in instruction RAM. Block transfer. 4 words of data are transferred from built-in instruction RAM to external memory. Conditional branch (if Lower) relative to PC. Conditional branch (if Less than or Equal) relative to PC. Conditional branch (if Less than) relative to PC. Conditional branch (if Negative) relative to PC. Conditional branch (if Not Carry) relative to PC. Conditional branch (if Not Equal) relative to PC. Conditional branch (if Not Higher) relative to PC. Conditional branch (if Not Lower) relative to PC. Conditional branch (if Not Overflow) relative to PC. Conditional branch (if Not Zero) relative to PC. Conditional branch (if Positive) relative to PC. Unconditional branch (Always) relative to PC. Return from fatal exception handling. Conditional branch (if Overflow) relative to PC. Conditional branch (if Zero) relative to PC. Inter-processor synchronization in multiprocessor system. ANDI imm16, reg1, reg2 V - 0 0 BE BGE disp9 disp9 III III - - - - - - - - BGT disp9 III - - - - BIST [reg2], [reg1] VII - - - - BL BLE disp9 disp9 III III - - - - - - - - BLT BN BNC BNE BNH BNL BNV disp9 disp9 disp9 disp9 disp9 disp9 disp9 III III III III III III III - - - - - - - - - - - - - - - - - - - - - - - - - - - - BNZ BP BR BRKRET BV BZ CAXI disp9 disp9 disp9 III III III IX - - - - - - - - - - - - - - - - - - - - - - - - disp9 disp9 disp16[reg1], reg2 III III VI 35 PD705101 Instruction CMP Operand(s) reg1, reg2 Format I CY OV S Z Function Comparison. reg2 is compared with reg1 sign-extended to a word and the condition flag is set according to the result. The comparison involves subtracting reg1 from reg2. Comparison. reg2 is compared with imm5 sign-extended to a word and the condition flag is set according to the result. The comparison involves subtracting imm5, sign-extended to a word, from reg2. DI II - - - - Disable interrupt. Maskable interrupts are disabled. DI instruction cannot disable nonmaskable interrupts. Division of signed operands. reg2 is divided by reg1 (signed operands). The quotient is stored in reg2 and the remainder in r30. The division is performed so that the sign of the remainder will match that of the dividend. DIVU reg1, reg2 I - 0 Division of unsigned operands. reg2 is divided by reg1 (unsigned operands). The quotient is stored in reg2 and the remainder in r30. The division is performed so that the sign of the remainder will match that of the dividend. Enable interrupt. Maskable interrupts are enabled. The EI instruction cannot enable nonmaskable interrupts. Processor halt. The processor is placed in sleep mode. Port input. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. A byte of data is read from the resulting port address, zero-extended to a word, then stored in reg2. Port input. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. A halfword of data is read from the produced port address, zero-extended to a word, and stored in reg2. Bit 0 of the unsigned 32-bit port address is masked to 0. Port input. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. A word of data is read from the resulting port address, then written into reg2. Bits 0 and 1 of the unsigned 32-bit port address are masked to 0. imm5, rag2 II DIV reg1, reg2 I - EI II - - - - HALT IX - - - - IN.B disp16[reg1], reg2 VI - - - - IN.H disp16[reg1], reg2 VI - - - - IN.W disp16[reg1], reg2 VI - - - - 36 PD705101 Instruction JAL Operand(s) disp26 Format IV CY - OV - S - Z - Function Jump and link. The sum of the current PC and 4 is written into r31. disp26, sign-extended to a word, is added to the PC and the sum is set to the PC for control transfer. Bit 0 of disp26 is masked. Indirect unconditional branch via register. Control is passed to the address designated by reg1. Bit 0 of the address is masked to 0. JR disp26 IV - - - - Unconditional branch. disp26, sign-extended to a word, is added to the current PC and control is passed to the address specified by that sum. Bit 0 of disp26 is masked to 0. LD.B disp16[reg1], reg2 VI - - - - Byte load. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. A byte of data is read from the produced address, sign-extended to a word, then written into reg2. LD.H disp16[reg1], reg2 VI - - - - Halfword load. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. A halfword of data is read from the produced address, sign-extended to a word, then written into reg2. Bit 0 of the unsigned 32-bit address is masked to 0. Word load. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. A word of data is read from the produced address, then written into reg2. Bits 0 and 1 of the unsigned 32-bit address are masked to 0. Load into system register. The contents of reg2 are set in the system register identified by the system register number (regID). Saturatable operation on signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers and the product is added to reg3. [If no overflow has occurred:] The result is stored in reg3. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. JMP [reg1] I - - - - LD.W disp16[reg1], reg2 VI - - - - LDSR reg2, regID II MAC3 reg1, reg2, reg3 VIII - - - - 37 PD705101 Instruction MACI Operand(s) imm16, reg1, reg2 Format V CY - OV - S - Z - Function Sum-of-products operation on signed 32-bit operands. reg1 and imm16, sign-extended to 32 bits, are multiplied together as signed integers and the product is added to reg2 as a signed integer. [If no overflow has occurred:] The result is written into reg2. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg2; if the result is negative, the negative maximum is written into reg2. MACT3 reg1, reg2, reg3 VIII - - - - Saturatable operation on signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers and the high-order 32 bits of the product are added to reg3 as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. MAX3 reg1, reg2, reg3 VIII - - - - Maximum. reg2 and reg1 are compared as signed integers. The larger value is written into reg3. Minimum. reg2 and reg1 are compared as signed integers. The smaller value is written into reg3. Data transfer. reg1 is copied to reg2 for data transfer. Data transfer. imm5, sign-extended to a word, is copied into reg2 for data transfer. Addition. The high-order 16 bits (imm16), sign-extended to a word, are added to reg1 and the sum is written into reg2. Addition. A word consisting of the high-order 16 bits (imm16) and low-order 16 bits (0) is added to reg1 and the sum is written into reg2. Multiplication of signed operands. reg2 and reg1 are multiplied together as signed values. The high-order 32 bits of the product (double word) are written into r30 and low-order 32 bits are written into reg2. Multiplication of signed 32-bit operands. reg2 and reg1 are multiplied together as signed integers. The high-order 32 bits of the product are written into reg3. MIN3 reg1, reg2, reg3 VIII - - - - MOV reg1, reg2, I - - - - imm5, reg2 II - - - - MOVEA imm16, reg1, reg2 V - - - - MOVHI imm16, reg1, reg2 V - - - - MUL reg1, reg2 I - MUL3 reg1, reg2, reg3 VIII - - - - 38 PD705101 Instruction MULI Operand(s) imm16, reg1, reg2 Format V CY - OV - S - Z - Function Saturatable multiplication of signed 32-bit operands. reg1 and imm16, sign-extended to 32 bits, are multiplied together as signed integers. [If no overflow has occurred:] The result is written into reg2. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg2; if the result is negative, the negative maximum is written into reg2. MULT3 reg1, reg2, reg3 VIII - - - - Saturatable multiplication of signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers. The high-order 32 bits of the product are written into reg3. MULU reg1, reg2 I - Multiplication of unsigned operands. reg1 and reg2 are multiplied together as unsigned values. The high-order 32 bits of the product (double word) are written into r30 and the low-order 32 bits are written into reg2. No operation. NOT. The NOT (ones complement) of reg1 is taken and written into reg2. OR. The OR of reg2 and reg1 is taken and written into reg2. OR. The OR of reg1 and imm16, zeroextended to a word, is taken and written into reg2. Port output. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. The low-order one byte of the data in reg2 is output to the resulting port address. Port output. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. The low-order two bytes of the data in reg2 are output to the resulting port address. Bit 0 of the unsigned 32-bit port address is masked to 0. Port output. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. The word of data in reg2 is output to the produced port address. Bits 0 and 1 of the unsigned 32-bit port address are masked to 0. Return from trap/interrupt handling routine. The return PC and PSW are read from the system registers so that program execution will return from the trap or interrupt handling routine. NOP NOT reg1, reg2 III I - - - 0 - - OR reg1, reg2 I - 0 ORI imm16, reg1, reg2 V - 0 OUT.B reg2, disp16[reg1] VI - - - - OUT.H reg2, disp16[reg1] VI - - - - OUT.W reg2, disp16[reg1] VI - - - - RETI IX 39 PD705101 Instruction SAR Operand(s) reg1 ,reg2 Format I CY OV 0 S Z Function Arithmetic right shift. reg2 is arithmetically shifted to the right by the displacement specified by the low-order five bits of reg1 (MSB value is copied to the MSB in sequence). The result is written into reg2. Arithmetic right shift. reg2 is arithmetically shifted to the right by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. SATADD3 reg1, reg2, reg3 VIII Saturatable addition. reg1 and reg2 are added together as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. SATSUB3 reg1, reg2, reg3 VIII Saturatable subtraction. reg1 is subtracted from reg2 as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. SETF imm5, reg2 II - - - - Set flag condition. reg2 is set to 1 if the condition specified by the low-order four bits of imm5 matches the condition flag; otherwise it is set to 0. Logical left shift. reg2 is logically shifted to the left (0 is put on the LSB) by the displacement specified by the low-order five bits of reg1. The result is written into reg2. imm5, reg2 II 0 Logical left shift. reg2 is logically shifted to the left by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. Left shift of concatenation. The 64 bits consisting of reg3 (high order) and reg2 (low order) are logically shifted to the left by the displacement specified by the low-order five bits of reg1. The high-order 32 bits of the result are written into reg3. imm5, reg2 II 0 SHL reg1, reg2 I 0 SHLD3 reg1, reg2, reg3 VIII - - - - 40 PD705101 Instruction SHR Operand(s) reg1, reg2 Format I CY OV 0 S Z Function Logical right shift. reg2 is logically shifted to the right by the displacement specified by the low-order five bits of reg1 (0 is put on the MSB). The result is written into reg2. Logical right shift. reg2 is logically shifted to the right by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. SHRD3 reg1, reg2, reg3 VIII - - - - Right shift of concatenation. The 64 bits consisting of reg3 (high order) and reg2 (low order) are logically shifted to the right by the displacement specified by the low-order five bits of reg1. The low-order 32 bits of the result are written into reg3. ST.B reg2, disp16[reg1] VI - - - - Byte store. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. The low-order one byte of data in reg2 is stored at the resulting address. VI - - - - Halfword store. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. The low-order two bytes of the data in reg2 are stored at the resulting address. Bit 0 of the unsigned 32-bit address is masked to 0. Word store. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. The word of data in reg2 is stored at the resulting address. Bits 0 and 1 of the unsigned 32-bit address are masked to 0. Processor stop. The processor is placed in stop mode. System register store. The contents of the system register identified by the system register number (regID) are set in reg2. Subtraction. reg1 is subtracted from reg2. The difference is written into reg2. Software trap. The return PC and PSW are saved in the system registers: PSW.EP = 1 Save in FEPC, FEPSW PSW.EP = 0 Save in EIPC, EIPSW The exception code is set in the ECR: PSW.EP = 1 Set in FECC PSW.EP = 0 Set in EICC PSW flags are set: PSW.EP = 1 Set NP and ID PSW.EP = 0 Set EP and ID Program execution jumps to the trap handler address corresponding to the trap vector (0-31) specified by vector and begins exception handling. imm5, reg2 II 0 ST.H reg2, disp16[reg1] ST.W reg2, disp16[reg1] VI - - - - STBY IX - - - - STSR regID,reg2 II - - - - SUB reg1,reg2 I TRAP vector II - - - - 41 PD705101 Instruction XOR Operand(s) reg1,reg2 Format I CY - OV 0 S Z Function Exclusive OR. The exclusive OR of reg2 and reg1 is taken and written into reg2. Exclusive OR. The exclusive OR of reg1 and imm16, zero-extended to a word, is taken and written into reg2. XORI imm16, reg1,reg2 V - 0 42 PD705101 16. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25C) Parameter Power supply voltage Input voltage Clock input voltage Operating ambient temperature Storage temperature Symbol VDD VI VK VA Tstg Conditions Rating -0.5 to +4.5 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -40 to +85 -65 to +150 Unit V V V C C Cautions 1. Do not connect an output (or input/output) pin of an IC device directly to any other output (or input/output) pin of the same device. Do not connect the VDD or VCC pin of an IC device directly to its GND pin or a ground. Note, however, that these restrictions do not apply to the highimpedance pins of an external circuit, whose timing has been specifically designed to avoid output collision. 2. Absolute maximum ratings are rated values, beyond which physical damage may be caused to the product; if the rated value of any of the parameters in the above table is exceeded even momentarily, the quality of the product may deteriorate. Always use the product within its rated values, therefore. For IC products, normal operation and quality are guaranteed only when the ratings and conditions described under the DC and AC characteristics are satisfied. DC CHARACTERISTICS (TA = -40 to +85C, VDD = 3.0 to 3.6 V) Parameter Low-level clock input voltage High-level clock input voltage Low-level input voltage High-level input voltage Low-level shmitt input voltage High-level shmitt input voltage Low-level output voltage High-level output voltage Low-level input leakage current High-level input leakage current Low-level output leakage current High-level output leakage current Supply currentNote 3 Symbol VKL VKH VIL VIH VSL VSH VOL VOH ILIL ILIH ILOL ILOH IDD Note 2 Note 2 IOL = 3.2 mA IOH = -400 A VI = 0 V VIN = VDD VO = 0 V VO = VDD When operating At HALT mode At STOP modeNote 4 167 45 36 0.85 VDD -10 10 -10 10 230 60 180 Conditions Note 1 Note 1 MIN. -0.5 0.8 VDD -0.5 2.0 -0.5 0.8 VDD TYP. MAX. +0.2 VDD VDD + 0.3 +0.6 VDD + 0.3 +0.2 VDD VDD + 0.3 0.4 Unit V V V V V V V V A A A A mA mA A Notes 1. X2 pin and SCLK pin at external clock input 2. PORT0/SCLK, PORT2/SI, RXD 3. Supply current at f = 33 MHz, when output pins are open. 4. External clock mode when clock input is stopped. 43 PD705101 CAPACITANCE (TA = -40 to +85C, VDD = 3.0 to 3.6 V) Parameter Input capacitance I/O capacitance Symbol CI CIO fC = 1 MHz Conditions MIN. MAX. 15 15 Unit pF pF Remark These parameters are sample values, not the value actually measured. AC CHARACTERISTICS (TA = -40 to +85C, VDD = 3.0 to 3.6 V) AC test input waveform VDD 2.0 V 0.5 VDD 0V 4 ns Test point 0.6 V AC test output waveform 0.85 VDD 0.5 VDD Test points 0.4 V Test load V831 output pin CL = 50 pF 44 PD705101 (1) Clock input (X2) timing (when external clock used) Parameter External clock cycle Symbol <1> tCYX Conditions Stability of input clock is 0.1% or less tCYX MIN. 30 MAX. 60 Unit ns External clock high-level time External clock low-level time External clock rise time External clock fall time <2> <3> <4> <5> tXXH tXXL tXR tXF 10 10 5 5 ns ns ns ns <1> <2> 0.8 VDD X2 (input) 0.5 VDD 0.2 VDD <3> <5> <4> (2) Clock output timing (CLKOUT) Parameter External clock cycle External clock high-level time External clock low-level time External clock rise time External clock fall time Symbol <6> <7> <8> <9> tCYK tKKH tKKL tKR Conditions MIN. 30 tCYK/2 - 4 tCYK2 - 4 4 4 MAX. 60 Unit ns ns ns ns ns <10> tKF <6> <7> 0.8 VDD CLKOUT (output) 0.5 VDD 0.2 VDD <8> <10> <9> 45 PD705101 (3) Reset timing Parameter Symbol Conditions MIN. MAX. 2 7 7 Note 1 Note 2 Note 3 20 10 25 Unit RESET hold time (vs. VDD VALID) <11> tHVR RESET setup time (vs. BCLK) RESET hold time (vs. BCLK) RESET pulse low-level width <12> tSRK <13> THKR <14> tWRL s ns ns ms ms tCYK Notes 1. At power application or when returned from STOP mode, and the internal clock is generated. 2. At power application or when returned from STOP mode, and the internal clock is generated, after clock has stabilized. 3. When clock has stabilized under conditions other than Notes 1 and 2. Remark It is not necessary to satisfy tSRK and tHKR if reset during the period of tHVR. In such a case, however, the reset acknowledge timing may be shifted. VDD 0.9 VDD <11> <12> CLKOUT (output) <13> RESET (input) <14> <12> 46 PD705101 (4) DRAM access timing Parameter BCYST delay time (vs. CLKOUT) Address delay time (vs. CLKOUT) RAS delay time (vs. CLKOUT) CAS delay time (vs. CLKOUT) CAS signal interval CAS high-level time CAS low-level time CAS rise time CAS fall time WE delay time (vs. CLKOUT) OE delay time (vs. CLKOUT) REFRQ delay time (vs. CLKOUT) Data input setup time (DRAM read) (vs. CLKOUT) Data input hold time (DRAM read) (vs. CLKOUT) Symbol <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> tDKBC tDKA tDKRAS tDKCAS tCYC tCCH tCCL tCR tCF tDKWE tDKOE tDKREF tSDRMK tHKDRM tDKDT tLZKDT tHZKDT 2 2 2 0 5 2 2 3 10 10 20 Conditions MIN. 2 2 1 1 26 11 11 4 4 10 10 10 MAX. 10 9 6 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data output delay time (from active, vs. CLKOUT) <29> Data output delay time (from float, vs. CLKOUT) Data float delay time (vs. CLKOUT) <30> <31> (a) xxCAS signal <19> <22> <23> <20> 0.8 VDD xxCAS (output) 0.5 VDD 0.2 VDD <21> Remark xxCAS : UUCAS, ULCAS, LUCAS, LLCAS 47 PD705101 (b) CBR refresh, CBR self refresh timing CLKOUT (output) <17> <17> <17> RAS (output) <18> xxCAS (output) <18> <26> REFRQ (output) <26> 48 PD705101 (c) DRAM single 1-clock CAS off-page cycle (32-bit data bus) EDO off-page Trm CLKOUT (output) Trp Trc Tc Tce <15> <15> <15> BCYST (output) <16> <16> <16> <16> A1-A23 (output) RA CA <17> <17> <17> RAS (output) <18> xxCAS (output) <24> <24> WE (output) <25> <25> OE (output) <27> <28> D0-D31 (input) <30> D0-D31 (output) <31> Remark The dotted lines indicate high impedance. 49 PD705101 (d) DRAM single 1-clock CAS on-page cycle (32-bit data bus) EDO on-page Tc CLKOUT (output) Tce <15> <15> <15> BCYST (output) <16> CA <16> A1-A23 (output) <17> RAS (output) <18> xxCAS (output) <24> <24> WE (output) <25> <25> OE (output) <27> <28> D0-D31 (input) <29> D0-D31 (output) <31> <30> D0-D31 (output) <31> Remark The dotted lines indicate high impedance. 50 PD705101 (e) DRAM single 2-clock CAS off-page cycle (32-bit data bus) EDO off-page Trm CLKOUT (output) Trp Trc Tca Tcn Tce <15> <15> <15> BCYST (output) <16> <16> <16> <16> A1-A23 (output) RA CA <17> <17> <17> RAS (output) <18> <18> xxCAS (output) <24> <24> WE (output) <25> <25> OE (output) <27> D0-D31 (input) <28> <30> <31> D0-D31 (output) Remark The dotted lines indicate high impedance. 51 PD705101 (f) DRAM single 2-clock CAS on-page cycle (32-bit data bus) EDO on-page Tca CLKOUT (output) Tcn Tce <15> <15> <15> BCYST (output) <16> <16> A1-A23 (output) CA <17> RAS (output) <18> <18> xxCAS (output) <24> <24> WE (output) <25> <25> OE (output) <27> D0-D31 (input) <28> <29> <31> D0-D31 (output) <30> D0-D31 (output) <31> Remark The dotted lines indicate high impedance. 52 PD705101 (g) DRAM burst 1-clock CAS off-page cycle (32-bit data bus) EDO off-page Trm CLKOUT (output) <15> <15> <15> Trp Trc Tc Tc2 Tc3 Tc4 Tce BCYST (output) <16> A1-A23 (output) <16> RA <16> CA1 <16> CA2 <16> CA3 <16> CA4 <16> <17> RAS (output) <17> <17> <18> xxCAS (output) <24> WE (output) <18> <18> <16> <24> <25> <25> OE (output) <27> <28> D0-D31 (input) <30> D0-D31 (output) 1 <29> 2 1 <29> 3 <27> <28> 2 <29> 4 <27><28> <27> <28> 3 <31> 4 Remark The dotted lines indicate high impedance. 53 PD705101 (h) DRAM burst 2-clock CAS off-page cycle (32-bit data bus) Trm CLKOUT (output) Trp Trc Tca Tcn1 Tca2 Tcn2 Tca3 Tcn3 Tca4 Tcn4 Tce <15> BCYST (output) <16> A1-A23 (output) <16> RA <16> <15> <15> <15> <15> <15> <15> <15> <15> <16> CA1 CA2 <16> CA3 <16> CA4 <16> <17> RAS (output) <17> <17> <18> <18> <18> <18> <18> <18> <18> <18> xxCAS (output) <24> WE (output) <24> <25> <25> OE (output) <27><28> D0-D31 (input) <30> D0-D31 (output) 1 1 <29> 2 <27><28> 2 <29> 3 <27><28> 3 <29> 4 <27><28> 4 <31> Remark The dotted lines indicate high impedance. 54 PD705101 (5) SRAM (ROM), Page-ROM, I/O access timing Parameter BCYST delay time (vs. CLKOUT) Address delay time (vs. CLKOUT) Symbol <15> <16> tDKBC tDKA tDKDT tLZKDT tHZKDT tDKCS tDKRD tDKWR tDKMRD tDKMWR tSDTK tHKDT tSRYK tHKRY Conditions MIN. 2 2 2 2 3 2 2 2 2 2 4 1 7 3 MAX. 10 9 10 10 20 10 10 10 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data output delay time (from active, vs. CLKOUT) <29> Data output delay time (from float, vs. CLKOUT) Data float delay time (vs. CLKOUT) CS delay time (vs. CLKOUT) IORD output delay time (vs. CLKOUT) IOWR output delay time (vs. CLKOUT) MRD output delay time (vs. CLKOUT) xxMWR delay time (vs. CLKOUT) Data input setup time (vs. CLKOUT) Data input hold time (vs. CLKOUT) READY setup time (vs. CLKOUT) READY hold time (vs. CLKOUT) <30> <31> <32> <33> <34> <35> <36> <37> <38> <39> <40> 55 PD705101 (a) I/O access timing Ta Ts Ts CLKOUT (output) <15> <15> <15> BCYST (output) <16> <16> A1-A23 (output) <32> <32> CS (output) <33> <33> IORD (output) <37> <38> D0-D31 (input) <34> <34> IOWR (output) <29> <29> D0-D31 (output) <30> <31> D0-D31 (output) <39> <40> <39> <40> READY (input) Remark The dotted lines indicate high impedance. 56 PD705101 (b) SRAM (ROM)/Page-ROM single cycle Ta Ts Ts CLKOUT (output) <15> <15> <15> BCYST (output) <16> <16> A1-A23 (output) <32> <32> CS (output) <35> <35> MRD (output) <37> <38> D0-D31 (input) <36> <36> xxMWR (output) <29> <29> D0-D31 (output) <30> <31> D0-D31 (output) <39> <40> <39> <40> READY (input) Remark The dotted lines indicate high impedance. 57 PD705101 (c) Page-ROM burst cycle (32-bit data bus) Ta CLKOUT (output) <15> BCYST (output) <16> A1-A23 (output) <32> CS1-CS7 (output) <33> MRD (output) Tb1 Tb1 Ta2 Tb2 Ta3 Tb3 Ta4 Ts <15> <15> <15> <15> <15> <15> <15> <16> <16> <16> <32> <33> <37><38> D0-D31 (input) <39> <40> <39> <40> READY (input) <37> <38> <37> <38> <37> <38> <39> <40> <39> <40> <39> <40> Remark The dotted lines indicate high impedance. 58 PD705101 (6) Interrupt timing Parameter NMI setup time (vs. CLKOUT) NMI hold time (vs. CLKOUT) INTPxx setup time (vs. CLKOUT) INTPxx hold time (vs. CLKOUT) NMI clock high-level time NMI clock low-level time Symbol <41> tSNK <42> tHKN <43> tSIK <44> tHKI <45> tNMH <46> tNML Conditions MIN. 5 7 7 3 5T+12 5T+12 MAX. Unit ns ns ns ns ns ns Remark T = tCYK (external clock cycle) CLKOUT (output) <41> 2.0 V NMI (input) 0.5 VDD 0.6 V <46> <42> <42> <41> <45> <43> INTP00-INTP03, INTP10-INTP13 (input) <44> 59 PD705101 (7) Bus hold timing Parameter Data active delay time (vs. CLKOUT) Data float delay time (vs. CLKOUT) HLDRQ input setup time (vs. CLKOUT) HLDRQ hold time (vs. CLKOUT) HLDAK output delay time Address float delay time (vs. CLKOUT) Address active delay time (vs. CLKOUT) Symbol <30> tLZKDT <31> tHZKDT <47> tSHQK <48> tHKHQ <49> tDKHA <50> tHZKA <51> tLZKA Conditions MIN. 2 3 7 3 2 3 2 10 20 10 MAX. 10 20 Unit ns ns ns ns ns ns ns Ti CLKOUT (output) Th Th Th Th Ti <47> HLDRQ (input) <49> HLDAK (output) <50> <48> <47> <49> <51> Note (output) <31> <30> D0-D31 (output) Note BCYST, WE, OE, A1-A23, CS1-CS7, RAS, xxCAS, MRD, IORD, xxMWR, IOWR Remark The dotted lines indicate high impedance. 60 PD705101 (8) DMA timing Parameter DMARQ input setup time (vs. CLKOUT) DMARQ hold time (vs. CLKOUT) DMAAK output delay time Symbol <52> tSDQK <53> tHKDQ <54> tDKDAK Conditions MIN. 7 3 2 10 MAX. Unit ns ns ns CLKOUT (output) <52> DMARQ0-DMARQ3 (input) <53><52> <54> DMAAK0-DMAAK3 (output) <54> 61 PD705101 (9) CSI timing (a) SCLK input mode Parameter SCLK cycle SCLK high-level time SCLK low-level time SCLK rise time SCLK fall time SI input setup time (vs. SCLK) SI input hold time (vs. SCLK) SO output delay time (vs. SCLK) Symbol <55> tCYSI <56> tSIH <57> tSIL <58> tSIR <59> tSIF <60> tSDTS <61> tHSDT <62> tDSDT 30 30 2 30 Conditions MIN. 120 50 50 10 10 MAX. Unit ns ns ns ns ns ns ns ns <55> <56> SCLK (input) 0.8 VDD 0.5 VDD 0.2 VDD <60> SI (input) <62> <61> <57> <58> <59> SO (output) 62 PD705101 (b) SCLK output mode Parameter SCLK cycle SCLK high-level time SCLK low-level time SCLK rise time SCLK fall time SI input setup time (vs. SCLK) SI input hold time (vs. SCLK) SO output delay time (vs. SCLK) Symbol <63> tCYSO <64> tSOH <65> tSOL <66> tSOR <67> tSOF <68> tSDTS <69> tHSDT <70> tDSDT 30 30 2 30 Conditions MIN. 120 50 50 10 10 MAX. Unit ns ns ns ns ns ns ns ns <63> <64> SCLK (output) 0.8 VDD 0.5 VDD 0.2 VDD <68> SI (input) <70> <69> <65> <66> <67> SO (output) 63 PD705101 (10) Timer timing Parameter TI clock cycle TI clock high-level time TI clock low-level time TI clock rise time TI clock fall time TCLR clock high-level time TCLR clock low-level time Symbol <71> tCYT <72> tTIH <73> tTIL <74> tTR <75> tTF <76> tCLH <77> tCLL 4T + 10 4T + 10 Conditions MIN. 243 4T + 10 4T + 10 10 10 MAX. Unit ns ns ns ns ns ns ns Remark T = tCYK (external clock cycle) <71> <72> 2.0 V TI (input) 0.5 VDD 0.6 V <76> 2.0 V TCLR (input) 0.6 V <77> <73> <74> <75> 64 PD705101 17. PACKAGE DRAWINGS 160 PIN PLASTIC LQFP (FINE PITCH) ( 24) A B 120 121 81 80 detail of lead end C D S Q R 160 1 41 40 F G P H I M J K M N NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 26.00.2 24.00.2 24.00.2 26.00.2 2.25 2.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145+0.055 -0.045 0.10 1.40.1 0.1250.075 3 +7 -3 1.7 MAX. INCHES 1.024 +0.008 -0.009 0.9450.008 0.9450.008 1.024 +0.008 -0.009 0.089 0.089 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.0550.004 0.0050.003 3 +7 -3 0.067 MAX. S160GM-50-8ED-2 65 PD705101 18. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the PD705101. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 18-1. Soldering Conditions for Surface-Mount Devices Soldering Process Infrared ray reflow Soldering Conditions Peak package's surface temperature: 235 C Reflow time: 30 seconds or less (210 C or more) Maximum allowable number of reflow processes: 2 Exposure limit: 3 daysNote (10 hours of pre-baking is required at 125 C afterward) VPS VP15-103-2 Partial heating method - Note Maximum number of days during which the product can be stored at a temperature of 25 C and a relative humidity of 65 % or less after dry-pack package is opened. Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). 66 PD705101 [MEMO] 67 PD705101 [MEMO] 68 PD705101 [MEMO] 69 PD705101 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 70 PD705101 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829 J97. 8 71 PD705101 The related documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. V830, V831, and V830 Family are trademarks of NEC Corporation. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 72 |
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